SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01  27 January 2010
13 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
 
7.9   SMBus/I
2
C-bus interface
The data registers in this device are selected by the Pointer Register. At power-up, the
Pointer Register is set to 00h, the location for the Capability Register. The Pointer
Register latches the last location to which it was set. Each data register falls into one of
three types of user accessibility:
" Read only
"  Write only
"  Write/Read same address
A write to this device will always include the address byte and the pointer byte. A write to
any register other than the Pointer register requires two data bytes.
Reading this device can take place either of two ways:
"  If the location latched in the Pointer register is correct (most of the time it is expected 
that the Pointer register will point to one of the Temperature register (as it will be the
data most frequently read), then the read can simply consist of an address byte,
followed by retrieving the two data bytes.
"  If the Pointer register needs to be set, then an address byte, pointer byte, 
repeat START, and another address byte will accomplish a read.
The data byte has the most significant bit first. At the end of a read, this device can accept
either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge
is typically used as a signal for the slave that the Master has read its last byte). It takes
this device 125 ms to measure the temperature. Refer to timing diagrams Figure 6
 to
Figure 9
 for how to program the device.
 
Fig 5.    How SE97B responds to SMBus Alert Response Address
0
0
0
1
1
A2
Alert Response Address
1
1
0
0
S
0
0
0
START bit
read
acknowledge
002aac685
A1
A0
0
1
P
device address
no acknowledge
STOP bit
host NACK and
sends a STOP bit
Slave acknowledges and
sends its slave address.
The last bit of slave address
is hard coded '0'.
master sends a START bit,
ARA and a read command
host detects
SMBus ALERT
1
A = ACK = Acknowledge bit. W = Write bit = 0. R = Read bit = 1.
Fig 6.    SMBus/I
2
C-bus write to the Pointer register
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
A6
A5
A4
A3
A2
A1
A0
SDA
D7
D6
D5
D4
D3
D2
D1
D0
device address and write
register address
W
A
S
START
ACK
by device
P
STOP
A
ACK
by device
002aab308
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